May 6, 2018

VLSI Project: The Beta Layout [help needed]

Current Tasks:
►Complete 32-bit ALU layout [unpipelined] in a 3-metal-layer C5 process.
►Extend Excel VBA macro to generate code for sequential instructions (machine language to actual electrical signals).

Current Obstacles/Unresolved Decisions:
►Use of complementary CMOS or pass transistor logic (do both? time expensive, will depend on sched.
►Adder selection: Brent-Kung; Kogge Stone; Ladner Fischer (brent takes up most space but seems to be fastest, consider fan-out) [do all? time expensive, will depend on sched.)
►layout requirements and DRC errors

Please leave a comment on the post below for advise. Any help is highly appreciated.

Facing difficulty in doing problems on stack detective

I am not able to do these problems properly, it's very rare that I get answers on the first try. What would you recommend me to do, like going through the lectures again or some resources over then web or something else, because these problems seems interesting to me and would like to do them properly?

Practice with the tutorial problems.
I was having a hard time too, so I built a pdf of tutorial problem 5, printed it, then taped the pages together to get a clear view of the problem all at once. (so much easier this way)
Before doing this, I gave up after attempting 3 of tutorial problems, then worked on the lab. If you like to program, the I'd recommend working on the lab after getting acquainted with the calling, entrance and exit sequences found on page 15 of the beta docs, it gives a template for linkage procedure.
Slide #16 of procedures and stacks
Slide #19 of procedures and stacks
page 32-38 of the digital study guide

Also, coffee.

Error: Driven by Multiple Gates

I am getting an error that is not logical to me.
Node 8 is driven by multiple gates. See devices: mux2_7[2] mux2_7[1] mux2_7[0]
Node <x> is driven by multiple gates. See devices: <devices>

If you have replicated muxes (i.e., a mux with more than 1 bit of output), you'll have to set the bus width on its output (or alternately, give it a signal name with the right length, like X[2:0]). If you have it connected directly to another component, you'll have to add a wire in between.

Back-up Work Locally

Is it possible to import relevant files for our beta designs locally onto our computers?

Looks like the module clipboard saves its data in LocalStorage. If you just want to locally back up your data, try this:
Click the "save modules to module clipboard" button in Jade (the one with the down arrow)
Load up your browser's developer tools (usually F12).
Go to LocalStorage (in Chrome it's under the Resources tab)
There should be a key called "jade_saved_modules". Copy the corresponding value to your clipboard, and paste it into a text editor and save the file. Make sure you copy the entire value. The first time I tried in Chrome, it missed the beginning.
Then to load a backup, do steps 2 and 3, and paste the contents of the text file into the value for jade_saved_modules (note: doing this made Chrome's developer tools freeze for a bit, but it worked. Then click the "select modules to load from module clipboard" button in Jade.

I'd recommended saving your work before messing with this, just in case.

LE14.3.4 CACHE COMPARISONS Part C: Why maps - in cache C1 - the fetch of word 256 to line 0, etc.?

The explanation states:
The benchmark has a loop containing 5 instructions and 3 data fetches. In cache C1, the direct mapped cache, the fetch of word 256 maps to line 0, 257 to line 1, and 258 to line 2. The instructions in the loop are at lines 1-5. This means that there is a conflict between 2 of the data fetches and 2 of the instruction fetches. Therefore the hit rate is 4/8.

I do not understand why the fetch of word 256 maps to line 0, 257 to line 1, and 258 to line 2. Are those numbers 256 to 258 hex or decimal? Do we need to translate those numbers into their binaries to identify the mapped lines as index as had been illustrated in L14 slide #27 and #28? An explanation is appreciated. Thank you!

They're in decimal. Converting them to binary should make it clear why they map to those particular lines.
(This course may take it for a given that we know 256 = 2^8 = 0b100000000)



Consider a 2-way set-associative cache that has 16 cache lines in each of the two direct-mapped subcaches and a block size of 2 words (i.e., a miss brings in an even-odd word pair from main memory). To calculate the hit ratio about the snippet of code below. . = 0x2000 CMOVE(0x1000,R0) loop: LD(R0,0,R1) SUBC(R0,4,R0) BNE(R0,loop) HALT()
All the data fetches will be misses. I am confused - "If the block size was 1 word, then the data fetches would all be misses. However, because the block is of size 2. That means that every other data fetch will be a hit.". This is confusing. From my understanding, all the data are new, how can it be fetched from cache?

Since the block size is two words, each time there's a cache miss it loads a block of two words into the cache. So for addresses that are accessed sequentially, the first access to a given block will be a miss, but the second will be a hit (assuming the data is still in the cache by that time, which it is in this case). This happens regardless of the direction you're moving in.

For example, when you access 0x10 for the first time, the cache loads the corresponding block- 0x10 and 0x14 - from memory. Then when you access 0x14, it's already in the cache.

Or if you're going in the other direction, if you access 0x14 first, the cache loads that same block: 0x10 and 0x14. Then when you access 0x10, it's already in the cache. (If you're wondering why it's the same block, think about what those two locations look like in binary).

Does it mean that, if we have 2^n blocks, then we will have n-1 hits every n iterations of a loop in the long run?

Don't assume that the first address (that missed) was the first word in the block! If the first address was the last word in the block, for example, and the next memory address is in the next block, you would still get two misses in a row.

On  Sequential and Random Accesses

It is said that sequential and random access are related to the NOR and NAND gates. Could someone tell me what the relationship between them is?

The structure of the memory is similar to the CMOS structure of either a NOR gate (parallel) or a NAND gate (in series).

Here's some resources that explain it better than I can:
http://www.em.avnet.com/en-us/design/technical-articles/Pages/Articles/Understanding-the-Differences-Between-NAND-Flash-and-NOR-Flash-Memory-and-Key-Future-Trends.aspx (has a simple schematic showing what they mean by parallel vs series near the bottom of the page)



Word Alignment

What is "word alignment" at the bottom 2 bits? and why it is 00?

Word alignment just means that even though the beta uses byte addressing, we only access 32 bit words at a time so the bottom two bits should always be 0 to ensure that you are accessing a full word.